Principles of Verifiable RTL Design - A Functional Coding Style Supporting Verification Processes 豆 0.0分

资源最后更新于 2020-11-21 03:02:04

作者：Lionel Bening

出版社：Springer

出版日期：2000-01

ISBN：9780792377887

文件格式： pdf

标签： FPGA EECS

简介· · · · · ·

Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog explains how you can write Verilog to describe chip designs at the RT-level in a manner that cooperates with verification processes. This cooperation can return an order of magnitude improvement in performance and capacity from tools such as simulation and equivalenc...